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19-1433; Rev 1; 3/99
2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier
General Description
The MAX3866 combined transimpedance preamplifier and limiting postamplifier is intended for application in SDH/SONET systems operating at 2.488Gbps. It operates from a single +3.3V or +5V supply and provides a differential output signal. The differential outputs are each 50 reverse terminated (100 differential termination) for low-noise and high-speed signal performance. The small-signal bandwidth and noise performance is specified for a source capacitance of 0.5pF. When the MAX3866 is used with the PIN photodetector, sensitivities better than -22dBm can be achieved. The MAX3866 is equipped with a programmable TTL lossof-power (LOP) output.
Features
o Input Sensitivities Better than -22dBm (7.8Ap-p) o Overdrive Capability Better than +1.4dBm (2.5mAp-p) o Single +3.3V or +5V Supply o 165mW Power Dissipation (at 3.3V) o 1.8GHz Analog Input Bandwidth o Programmable Loss-of-Power Indicator o 100 Differential Output
MAX3866
Applications
SDH/SONET Transmission Systems PIN/Preamplifier Receivers 2.488Gbps ATM Receivers Regenerators for SDH/SONET
PART MAX3866E/D
Ordering Information
TEMP. RANGE (see Note) PIN-PACKAGE Dice
Note: Dice are designed to operate over a -40C to +120C junction temperature (Tj) range, but are tested and guaranteed at TA = +25C.
Pad Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
VCCS FIL PHOTODIODE 200
VCCD
OUT+ PREAMP LIMITING POSTAMP OUT-
Zo = 50
MAX3875
CLOCK AND DATA RECOVERY
IN+
MAX3866
CHF+ CHF RPD CHFPDC LOP INV
Zo = 50
________________________________________________________________ Maxim Integrated Products
1
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866
ABSOLUTE MAXIMUM RATINGS
VCCD Voltage .......................................................-0.5V to +7.0V VCCS Voltage ...............0 VCCS VCCD and if VCCD 3.13V then 3.13V VCCS VCCD CHF+, CHF-, FIL, INV, LOP Voltage .......-0.5V to (VCCD + 0.5V) IN-, IN+ Voltage.....................................................-0.5V to +1.0V CPD+, CPD- Voltage ................(VCCD - 1.6V) to (VCCD + 0.5V) OUT+, OUT- Voltage ................(VCCD - 1.1V) to (VCCD + 0.5V) IN Current.......................................................................0 to 3mA PDC Current..................................................................-1mA to 0 Operating Junction Temperature Range (Tj ).....-55C to +125C Storage Temperature Range .............................-60C to +160C Processing Temperature (Die).........................................+400C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCCD = VCCS = +3.3V 5% or VCCD = +5.0V 10%, VCCS = open, Tj = -40C to +120C, unless otherwise noted. Typical values are at +3.3V and Tj = +25C.) PARAMETER Supply Current Input Bias Voltage Differential Output Impedance LOP Output High Voltage LOP Output Low Voltage Differential Output Voltage Swing Output Common-Mode Voltage SYMBOL IVCC VIN ZOUT VOH VOL VOD VCM Load = 4.7k to VCCD (Note 7) Load = 4.7k to VCCD (Note 7) RL = 100 (differential), IIN 7Ap-p RL = 100 (differential) 100 145 VCCD - 0.12 90 VCCD - 0.1 CONDITIONS MIN TYP 50 0.84 105 MAX 73 0.95 120 VCCD 0.4 UNITS mA V V V mVp-p V
AC ELECTRICAL CHARACTERISTICS
(VCCD = VCCS = +3.3V 5% or VCCD = +5.0V 10%, VCCS = open, Tj = -40C to +120C, unless otherwise noted. Typical values are at +3.3V and Tj = +25C.) (Notes 1, 2) PARAMETER Small-Signal Bandwidth Input Sensitivity Input-Referred RMS Noise Low-Frequency Cutoff Power-Supply Rejection Ratio LOP Hysteresis LOP Assert Level LOP Deassert Level Output Edge Speed Pulse-Width Distortion Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: tr, tf PWD SYMBOL BW IIN NIN fL PSRR f 2MHz, 100mVp-p Electrical (Note 4), low LOP assert, RPD = 510 RPD = 510 RPD = 510 20% to 80% (Note 5) (Notes 5, 6) 50 21 25 3 0.9 8.0 70 80 30 2.5Gbps, 223 - 1 PRBS, BER 10-10, CIN = 0.5pF, Tj = +120C CIN = 0.5pF, Tj = +120C CONDITIONS MIN TYP 1.8 7.8 433 (Note 3) 566 100 MAX UNITS GHz Ap-p nA kHz dB dB A A ps ps
CIN = total capacitance on IN. AC parameters are guaranteed by design and characterization. See Typical Operating Characteristics for worst-case distribution. Hysteresis = 20 log (VDEASSERT / VASSERT). IIN = 2.5mA. PWD = [(2 * Pulse Width) - Period] / 2. External load not required for normal operation.
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier
Typical Operating Characteristics
(VCCD = VCCS = +3.3V, TA = +25C, unless otherwise noted.)
LOP ASSERT/DEASSERT vs. RPD
MAX3866 TOC01
MAX3866
PULSE-WIDTH DISTORTION vs. TEMPERATURE
MAX3866 TOC02
OUTPUT COMMON-MODE VOLTAGE vs. TEMPERATURE
3.45 COMMON-MODE VOLTAGE (V) 3.40 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3.00 OUTOUT+
MAX3866 toc03
90 80 ASSERT/DEASSERT (A) 70 60 50 40 30 20 10 0 10 100 RPD () DEASSERT ASSERT
16 14 12 PWD (ps) 10 8 6 4 2 IN+ = 100A 0 -60 -40 -20 0 20 40 60 80
3.50
100
-50
-30
-20
0
20
40
60
80
100
TEMPERATURE (C)
TEMPERATURE (C)
DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE
MAX3866 TOC04
SUPPLY CURRENT vs. TEMPERATURE
MAX3866 TOC05
OUTPUT VOLTAGE vs. INPUT CURRENT
135 OUTPUT VOLTAGE (mVp-p) 130 125 120 115 110 105 100
MAX3866 TOC06
150 DIFFERENTIAL OUTPUT VOLTAGE (mVp-p) 145 140 135 130 125 120 115 110 105 100 -60 -40 -20 0 20 40 60 80
100 90 SUPPLY CURRENT (mA) 80 70 60 50 40 30 3.47V
140
3.14V
100
-50
-30
-10
10
30
50
70
90
1
10
100 INPUT CURRENT (A)
1k
10k
TEMPERATURE (C)
TEMPERATURE (C)
PULSE-WIDTH DISTORTION vs. INPUT CURRENT
15 10 PWD (ps) 5 0 -5 -10 -15 -20 1 10 100 INPUT CURRENT (A) 1k 10k 20mV/ div
MAX3866 TOC07
ELECTRICAL EYE DIAGRAM
MAX3866 TOC08
ELECTRICAL EYE DIAGRAM
MAX3866 TOC09
20
INPUT = 8Ap-p, 2.5Gbps, 223-1PRBS RL = 100 DIFFERENTIAL
20mV/ div
INPUT = 2.5mAp-p, 2.5Gbps, 223-1PRBS RL = 100 DIFFERENTIAL
50ps
50ps
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866
Typical Operating Characteristics (continued)
(VCCD = VCCS = +3.3V, TA = +25C, unless otherwise noted.)
SMALL-SIGNAL IMPEDANCE vs. FREQUENCY
MAX3866 toc10
DISTRIBUTION OF ELECTRICAL SENSITIVITY (WORST CASE)
VCC = +3.14V TO +5.5V Tj = +120C
MAX3866 toc11
99 98 97 96 95 94 93 92 91 90 89 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) TRANSIMPEDANCE (20log (VOUTp-p/IN+))
30 25 PERCENT OF UNITS (%) 20 15 10 5 0
7.28
7.71
8.14
8.57
ELECTRICAL SENSITIVITY (Ap-p)
Pad Description
PAD NAME VCCS CHF+ CHFFIL GND IN+ INPDC INV CPDCPD+ OUTOUT+ LOP VCCD 4 FUNCTION Positive Supply Voltage of Input Stage. Apply +3.3V if VCCD = +3.3V. If VCCD > +3.47V, disconnect from supply and decouple to GND. External Filter Capacitor. A capacitor connected between CHF+ and CHF- is used for setting the low-frequency cutoff. External Filter Capacitor. A capacitor connected between CHF+ and CHF- is used for setting the low-frequency cutoff. On-Chip Resistor for Filtering Photodiode Supply Voltage (connected to VCCD on chip) Electrical Ground Signal Input No Connect The voltage at this node programs the gain of the power detector. Connect a resistor between PDC and INV to adjust the LOP threshold. Used for programming the gain of the power detector. Connect a resistor between PDC and INV to adjust the LOP threshold. Filter Node for Power Detector. A capacitor connected between CPD+ and CPD- will provide additional filtering to the rectifier output within the power detector. Filter Node for Power Detector. A capacitor connected between CPD+ and CPD- will provide additional filtering to the rectifier output within the power detector. Inverted Data-Signal Output Noninverted Data-Signal Output TTL Output, Loss-of-Power, active high Power-Supply Voltage
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier
Typical Operating Circuits
3.3V CHF 100nF 10nF CHFVCCS FIL IN+ INGND PDC RPD* 510 INV CPDOUTCPD+ 100nF RPD* 510 OUTCHF+ VCCD LOP 100nF CHFVCCS FIL OUT+ IN+ INGND PDC INV CPDOUTCPD+ 100nF OUTCHF+ VCCD LOP 100nF CHF 100nF 5.0V
MAX3866
MAX3866
OUT+
MAX3866
OUT+
OUT+
3.3V OPERATION * NOTE: IF LOP OPERATION IS NOT DESIRED, RPD = 0
5.0V OPERATION
Circuit Description
Data Path
The combined preamplifier and limiting postamplifier (Figure 1) accepts an input current from a photodiode attached to the input pad IN+. The transimpedance input amplifier stage converts the input current to an output voltage with a typical transimpedance of 1.4k. The second stage of the data path is an active highpass filter. This filter converts the single-ended input signal to a differential signal, eliminating the DC component and adding approximately 16dB of gain. The output of the highpass filter drives the power detector and limiting amplifier circuitry. The limiting amplifier circuit is the third stage of the data signal path. It amplifies and limits the differential input signal. The output stage is a differential pair with internal 50 load resistors. The limited output voltage is typically 145mVp-p.
The output voltage of the adjustable gain amplifier drives the combined rectifier and lowpass filter circuitry. The resulting DC voltage is fed to a Schmitt trigger, which generates a high-level output signal if the DC input signal is below the LOP assert level, thus causing an LOP condition on the LOP output.
Design Procedure
Power Supply
The complete amplifier is supplied by a single supply voltage, VCCD. For operation at 3.3V, the supply voltage is applied at both the VCCD and VCCS pins (see Typical Operating Circuit). For operation at 5.0V, the voltage is only applied at VCCD. In this case, VCCS is on-chip controlled to approximately 3.2V. In the 5.0V configuration, an external 10nF grounded capacitor is required at the VCCS pin.
Power Detector
The power detect circuit consists of an adjustable-gain amplifier and combined rectifier with a lowpass filter. The adjustable-gain amplifier is controlled by an op amp. The gain is adjusted by means of an external resistor connected between the PDC and INV pins.
External Filter Capacitor CHF The value of CHF affects the maximum speed at which the compensation loop adjusts the input offset current. CHF should be chosen between 10nF and 100nF. The loop should be as slow as possible to reduce patterndependent jitter. Maxim recommends a value of CHF = 100nF.
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866
CHF+ ICC CHF-
MAX3866
RF IN VCCS FIL VCCD GND VOLTAGE REGULATOR TIA HPF LIM OUT DATA SIGNAL PATH OUT+ OUT-
VREF
OP AMP
ADJ
RMS DETECTOR LOP RECTIFIER
INV RPD
PDC
CPD+
CPD-
Figure 1. Functional Diagram of the Combined Preamplifier and Limiting Postamplifier
Loss-of-Power Threshold
If the LOP function is desired, Maxim recommends RPD = 510. If the LOP function is not desired, RPD = 0 (shorted). See Figure 2 for LOP definitions. If desired, the LOP threshold can be adjusted (see Assert/ Deassert vs. RPD in the Typical Operating Characteristics.
INPUT CURRENT
External Filter Capacitor CPD The LF cutoff of the power detector can be reduced by adding external capacitance across the CPD pins. This capacitor is only needed when this circuit is operated at lower data rates and lower edge speeds. In this way, the remaining ripple of power detector output voltage is reduced.
MAX. DEASSERT
DEASSERT
HYSTERESIS > 3dB
ASSERT
MIN. ASSERT
Figure 2. Loss-of-Power Definitions with RPD = 510
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier
Internal Input/Output Schematics
VCCS VCCD
MAX3866
50
50 OUT+ OUTESD STRUCTURE
IN+ ESD STRUCTURE ESD STRUCTURE
IN-
GND GND
Figure 3. OUT Pads
Figure 4. IN Pads
VCCD
CHF+ CHF-
VCCD ESD STRUCTURE 200 FIL ESD STRUCTURES
GND
GND
Figure 5. FIL Pads
Figure 6. CHF Pads
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866
Internal Input/Output Schematics (continued)
VCCD
PDC VCCD
ESD STRUCTURE INV
ESD STRUCTURE
GND
GND
Figure 7. INV Pad
Figure 8. PDC Pad
VCCD
CPD+ CPD-
VCCD ESD STRUCTURE 10k
LOP
ESD STRUCTURES
GND
GND
Figure 9. LOP Pad
Figure 10. CPD Pad
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier
Applications Information
Converting Average Optical Power to Signal Amplitude
Many of the MAX3866's specifications relate to input signal amplitude. When working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. The relations given in Table 1 are helpful for converting optical power to input signal when designing with the MAX3866. In an optical receiver, the input current to the transimpedance amplifier can be found by multiplying the power relationships in Table 1 with the photodiode responsivity.
Table 1. Optical-Power Relations*
PARAMETER Average Power Extinction Ratio Optical Power of a "1" Optical Power of a "0" Signal Amplitude SYMBOL PAVE re P1 P0 PIN RELATION PAVE = (P0 + P1) / 2 re = P1 / P0
MAX3866
P1 = 2PAVE re
re + 1
P0 = 2PAVE / (re +1)
PIN = P1 - P0 = 2PAVE (re - 1)
(re + 1)
Wire Bonding
Make corrections to the die with gold wire only, using ball bonding techniques. Die pad size is 4mils (100m) square and die thickness is 12mils (~300m).
*Assuming a 50% average input mark density.
Layout Techniques
The MAX3866's performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on all data signals.
LOP GND
Pad Configuration
OUT+ GND OUT-
VCCD VCCD VCCS VCCS CHF+ CHF-
CPD+ CPDGND 0.066" GND (1.68mm) INV PDC
FIL GND IN+ IN- GND N.C. 0.057" (1.45mm)
TRANSISTOR COUNT: 851
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866
NOTES
10
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier
NOTES
MAX3866
11
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2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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